In electronic circuit applications where more than one output is tied to a single connecting line or common bus, the use of tristate output devices is required. By way of example, a prior art Fairchild Advanced Schottky TTL three state or tristate output control device is illustrated in FIG. 1. Several elements or stages can be identified in such a TTL tristate output gate. The pullup element for sourcing current from the higher level voltage and power supply V.sub.cc consists of transistors Q12 and Q13 forming a Darlington current source. The Darlington current source supplies current from power supply V.sub.cc to the output V.sub.out. The "pulldown" element or stage for sinking current and voltage from the output V.sub.out to ground consists of transistor Q14 with a conventional squaring network including transistor Q16 at its base. In the example of FIG. 1 the pulldown transistor Q14 also includes a turn off accelerating transistor Q15 and associated diodes for sinking Miller current and accelerating turn off of pull down transistor Q14 during transition from low to high at the output V.sub.out. Step up transistor Q10 is coupled in series with the phase splitter Q11 to increase the input threshold at the logic data input V.sub.in.
When a low level voltage, binary zero in positive logic, appears at the input V.sub.in, a high level voltage, binary one, appears at the output V.sub.out. In this state the pullup element Q12 and Q13 is conducting affording a low impedance path to the output from the high level voltage V.sub.cc. The pulldown element Q14 is nonconducting affording a high impedance path to the low level voltage or ground.
When a high level voltage binary logic one appears at the input V.sub.in, a low level voltage binary zero appears at the output V.sub.out. In this state the pullup element Q12 and Q13 is nonconducting affording a high impedance blocking path from the high level voltage V.sub.cc to the output. The pulldown element Q14 is conducting affording a low impedance path from the output to ground.
The third state or high impedance state of the tristate device illustrated in FIG. 1 is afforded by the output enable terminal OE. When a low level potential or binary zero from the enable gate appears at terminal OE the active elements of the tristate device are deprived of base drive current. Thus, terminal OE provides a low impedance path to ground and all transistors become nonconducting. In this high impedance third state both the pullup element and pulldown element exhibit high impedance to signals appearing at the output V.sub.out. With all the elements deprived of base current the output effectively becomes a high impedance to any exterior circuitry, for example, a common bus to which the output V.sub.out may be connected. In this condition the tristate output device will neither source nor sink current at the output V.sub.out and will behave effectively as if nothing were there. Such a tristate device is therefore particularly applicable and suitable for applications in which a plurality of output gates are tied together or coupled to a common bus structure. In such common bus applications only one output, that is only one of many output devices of the type illustrated in FIG. 1 coupled to the bus structure, determines the voltage (high or low) of the bus while the other outputs for the remaining gates are in the high impedance third state.
When a high level voltage binary one appears at the output enable terminal OE the output device functions as a bistate output device sinking or sourcing current at the output V.sub.out according to whether the pulldown or pullup element is conducting. It should be noted that the output device is inherently inverting as a binary zero at the input V.sub.in generates a binary one at the output V.sub.out and vice versa. As stated above only one such tristate output device of many coupled to the common bus is active at any one time.
The enable gate which delivers a high or low voltage signal, binary one or zero, to the output enable terminal OE is itself a bistate TTL gate. In order to relinquish the common bus, not shown, to another tristate output device which is actively passing logic data in a bistate mode, the enable gate must remain actively conducting through its own pulldown element. Thus, the enable gate pulldown element affords a low impedance path from the output enable terminal OE to ground, continuously sinking base current from the transistors of the tristate output device. It is essential that the enable gate remain continuously activated for sinking current in order to maintain the high impedance or high Z state and prevent interference with high and low signals on the bus.
In a bus system with multiple tristate output devices coupled to the single connecting line, it is common to "power down" the unused devices in the high Z state in order to reduce power consumption. A problem frequently occurs during such a power down transition with the high Z state output devices interfacing at the bus. During the power down and reduction in voltage the enable gate coupled to the tristate output device tends to turn off or deactivate before the elements of the tristate output device itself. Once the enable gate is deactivated and becomes nonconducting there is no longer a route to ground for the base drive current at the phase splitter transistor Q11 through the terminal OE. As a result there is a time interval during which the tristate output device phase splitter transistor Q11 and pull down element Q14 become conducting. The pulldown element Q14 affords a low impedance path to ground at the tristate output V.sub.out and therefore at the entire common bus affecting all other devices connected to the bus. The system reliability is therefore reduced during power down and power up voltage transitions at the power supply V.sub.cc.
A further discussion of tristate output devices can be found, for example, in U.S. Pat. No. 4,311,927, issued Jan. 19, 1982, assigned to the assignee of the present invention; in U.S. Pat. No. 4,287,433, also owned by the present assignee; and in the FAST DATA BOOK, published 1982 by Fairchild Camera and Instrument Corporation, Digital Products Division, 333 Western Avenue, South Portland, Me. 04106. The prior art known to applicants does not directly address the problem of loss of the high Z state and therefore loss of reliability in tristate output devices during power down, power up, and power out transitions in the common power supply.
In U.S. Pat. No. 4,104,734, assigned to the assignee of the present application, the problem of protecting volatile random access memory cells during drop in the power supply voltage is addressed. According to this patent, a threshold type circuit is provided for detecting a drop in the system power supply voltage and for turning off bias networks in a sequence making it impossible to write into or change the data in a memory cell. The memory cells are thus protected while the power supply voltage is reduced to the minimum cell current requirements for maintaining the cell contents.
Threshold activation and control circuits and concepts have never been applied however to the unique requirements of tristate output devices and their associated enable gate circuits. More generally, such threshold circuits and concepts have not been applied to interdependent logic gate output circuits and subcircuits. Nor would the threshold detecting circuit of U.S. Pat. No. 4,104,734 be of a type that could optimally be applied in such environments all as hereafter described.